Array substrate, display device having the same and method of manufacturing the same

ABSTRACT

An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/392,629, filed on Feb. 25, 2009, which is a divisional of U.S.application Ser. No. 11/779,534, filed Jul. 18, 2007, and now issued asU.S. Pat. No. 7,511,300 and claims priority from and the benefit ofKorean Patent Application No. 10-2006-0067979, filed on Jul. 20, 2006,which are all hereby incorporated by reference for all purposes as iffully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an array substrate, a display deviceincluding the array substrate, and a method of manufacturing the arraysubstrate. More particularly, the present invention relates to an arraysubstrate capable of decreasing line resistance and the occurrence ofline defects, a display device including the array substrate, and asimplified method of manufacturing the array substrate.

2. Discussion of the Background

An array substrate of a flat panel display device includes various linesfor transmitting signals, which are formed through thin film depositionprocesses.

In the flat panel display device, the length of the lines has beenincreased, and the thickness of the lines has been decreased, therebyincreasing the resistance of the lines.

In addition, the lines chemically react with an insulating substrate, aninsulating layer, oxygen, etc., so that the resistance of the lines isgreatly increased. Therefore, the image display quality is deteriorated.

Furthermore, when a metal layer is etched to form the lines, the etchinguniformity of the metal layer may be deteriorated, which may deterioratethe etching profile of the lines.

SUMMARY OF THE INVENTION

The present invention provides an array substrate capable of decreasingline resistance and the occurrence of line defects.

The present invention also provides a display device including the abovementioned array substrate.

The present invention also provides a simplified method of manufacturingthe array substrate.

The present invention discloses an array substrate including a switchingelement, a signal transmission line, a passivation layer, and a pixelelectrode. The switching element is on an insulating substrate. Thesignal transmission line is connected to the switching element andincludes a barrier layer, a conductive line, and a copper nitride layer.The barrier layer is on the insulating substrate. The conductive line ison the barrier layer and includes copper or copper alloy. The coppernitride layer covers the conductive line. The passivation layer coversthe switching element and the signal transmission line and includes acontact hole through which a drain electrode of the switching element ispartially exposed. The pixel electrode is on the insulating substrateand connected to the drain electrode of the switching element throughthe contact hole.

The present invention also discloses a display device including aswitching element, a signal transmitting line, a pixel electrode, apassivation layer, a liquid crystal layer, an opposite electrode, and anopposite insulating substrate. The switching element is on an insulatingsubstrate. The signal transmitting line is connected to the switchingelement. The signal transmitting line includes a barrier layer, aconductive line, and a copper nitride layer. The barrier layer is on theinsulating substrate. The conductive line is on the barrier layer andincludes copper or copper alloy. The copper nitride layer covers theconductive line. The pixel electrode is on the insulating substrate andis connected to a drain electrode of the switching element. Thepassivation layer covers the switching element and the signaltransmission line.

The liquid crystal layer is on the passivation layer. The oppositeelectrode is on the liquid crystal layer and faces the pixel electrode.The opposite insulating substrate is on the opposite electrode and facesthe insulating substrate.

The present invention also discloses a method of manufacturing an arraysubstrate that is provided as follows. A barrier layer is formed on aninsulating substrate. A gate line and a gate electrode are formed on thebarrier layer. The gate line includes copper or copper alloy and thegate electrode is connected to the gate line. Nitride plasma is appliedto the gate line and the gate electrode. A gate insulating layer isdeposited on the insulating substrate to cover the gate line and thegate electrode. A data line, a source electrode connected to the dataline, a drain electrode spaced apart from the source electrode, and asemiconductor pattern are formed on the gate insulating layer. Thesource electrode is connected to the data line and the drain electrodeis spaced apart from the source electrode. The semiconductor pattern ison the gate electrode between the source electrode and the drainelectrode.

The present invention discloses another method of manufacturing an arraysubstrate that is provided as follows. A gate line, a gate electrode,and a gate insulating layer are formed on an insulating substrate. Thegate electrode is connected to the gate line. The gate insulating layercovers the gate line and the gate electrode. A semiconductor pattern isformed on the gate insulating layer corresponding to the gate electrode.A data line, a source electrode, and a drain electrode are formed on thegate insulating layer. The data line includes copper or copper alloy.The source electrode is connected to the data line. The drain electrodeis spaced apart from the source electrode with respect to thesemiconductor pattern. Nitride plasma is applied to the data line, thesource electrode, and the drain electrode. A passivation layer isdeposited on the gate insulating layer to cover the semiconductorpattern, the data line, the source electrode, and the drain electrode.

The present invention discloses still another method of manufacturing anarray substrate that is provided as follows. A first barrier layer, afirst conductive layer, and a first copper nitride layer are depositedon an insulating substrate, in sequence. The first conductive layerincludes copper or copper alloy. The first barrier layer, the firstconductive layer, and the first copper nitride layer are patterned toform a gate line and a gate electrode connected to the gate line. A gateinsulating layer is deposited on the insulating substrate to cover thegate line and the gate electrode. A data line, a source electrode, adrain electrode, and a semiconductor pattern are formed on the gateinsulating layer. The source electrode is connected to the data line andthe drain electrode is spaced apart from the source electrode. Thesemiconductor pattern is on the gate electrode between the sourceelectrode and the drain electrode.

The present invention discloses yet another method of manufacturing anarray substrate that is provided as follows. A barrier layer is formedon an insulating substrate. A gate line and a gate electrode are formedon the barrier layer. The gate line includes copper or copper alloy andthe gate electrode is connected to the gate line. Hydrogen plasma isapplied to the gate line and the gate electrode. A first gas mixture isinjected into a chamber to form a first gate insulating layer on theinsulating substrate. The first gas mixture includes silane gas,nitrogen gas, and ammonia gas. The amount of silane gas in the first gasmixture is no more than about 6.43% by volume. A second gas mixture isinjected into the chamber to form a second gate insulating layer on theinsulating substrate. The second gas mixture includes silane gas,nitrogen gas, and ammonia gas. The amount of silane gas in the secondgas mixture is no less than about 6.43% by volume. A third gas mixtureis injected into the chamber to form a third gate insulating layer onthe insulating substrate. The third gas mixture includes silane gas,nitrogen gas, and ammonia gas. The amount of silane gas in the third gasmixture is no more than about 6.43% by volume. A data line, a sourceelectrode, a drain electrode, and a semiconductor pattern are formed onthe third gate insulating layer. The source electrode is connected tothe data line and the drain electrode is spaced apart from the sourceelectrode. The semiconductor pattern is on the gate electrode betweenthe source electrode and the drain electrode.

It is to be understood that both the foregoing and general descriptionand the following detailed description are exemplary and explanatory andare intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate exemplary embodiments of theinvention, and together with the description serve to explain theprinciples of the invention.

FIG. 1 is a plan view showing an array substrate in accordance with oneexemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line I-I′ of FIG. 1.

FIG. 3 is an enlarged cross-sectional view showing portion ‘A’ of FIG.2.

FIG. 4 is a cross-sectional view taken along line II-II′ of FIG. 1.

FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG.13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, and FIG. 19 arecross-sectional views showing a method of manufacturing the arraysubstrate of FIG. 1.

FIG. 20 is a cross-sectional view showing a display device in accordancewith another exemplary embodiment of the present invention.

FIG. 21 is a cross-sectional view showing an array substrate inaccordance with another embodiment of the present invention.

FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26 are cross-sectionalviews showing a method of manufacturing the array substrate shown inFIG. 21.

FIG. 27 is a cross-sectional view showing an array substrate inaccordance with another exemplary embodiment of the present invention.

FIG. 28 is a cross-sectional view showing an array substrate inaccordance with another exemplary embodiment of the present invention.

FIG. 29 is a cross-sectional view showing a display device in accordancewith another exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

The invention is described more fully hereinafter with reference to theaccompanying drawings, in which embodiments of the invention are shown.This invention may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.Rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventionto those skilled in the art. In the drawings, the size and relativesizes of layers and regions may be exaggerated for clarity.

It will be understood that when an element or layer is referred to asbeing “on,” “connected to” or “coupled to” another element or layer, itcan be directly on, directly connected to, or directly coupled to theother element or layer, or intervening elements or layers may bepresent. In contrast, when an element is referred to as being “directlyon,” “directly connected to” or “directly coupled to” another element orlayer, there are no intervening elements or layers present. Like numbersrefer to like elements throughout. As used herein, the term “and/or”includes any and all combinations of one or more of the associatedlisted items.

It will be understood that, although the terms first, second, third etc.may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another region, layer or section. Thus, a first element,component, region, layer or section discussed below could be termed asecond element, component, region, layer or section without departingfrom the teachings of the present invention.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a,” “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention. Assuch, variations from the shapes of the illustrations as a result, forexample, of manufacturing techniques and/or tolerances, are to beexpected. Thus, embodiments of the invention should not be construed aslimited to the particular shapes of regions illustrated herein but areto include deviations in shapes that result, for example, frommanufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe invention.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms, such as those defined in commonly useddictionaries, should be interpreted as having a meaning that isconsistent with their meaning in the context of the relevant art andwill not be interpreted in an idealized or overly formal sense unlessexpressly so defined herein.

Hereinafter, the present invention will be described in detail withreference to the accompanying drawings.

FIG. 1 is a plan view showing an array substrate in accordance with oneexemplary embodiment of the present invention. FIG. 2 is across-sectional view taken along line I-I′ of FIG. 1. FIG. 3 is anenlarged cross-sectional view showing portion ‘A’ of FIG. 2. FIG. 4 is across-sectional view taken along line II-II′ of FIG. 1.

Referring to FIG. 1, FIG. 2, and FIG. 4, the array substrate includes aninsulating substrate 120, a gate line 131, a data line 133, a gateinsulating layer 126, a passivation layer 116, and a pixel electrode112. Alternatively, the array substrate may include a plurality of gatelines, a plurality of data lines, and a plurality of pixel electrodes.

The insulating substrate 120 may include a transparent glass thattransmits light. The insulating substrate 120 may not include alkalineions. When the insulating substrate 120 includes alkaline ions, thealkaline ions may be dissolved in a liquid crystal layer (not shown) andmay decrease the resistance of the liquid crystal layer, which maydecrease the image display quality and the adhesive strength between asealant (not shown) and the insulating substrate 120. In addition,characteristics of a thin film transistor may be deteriorated.

The insulating substrate 120 may also include a high polymer that isoptically transparent. Examples of optically transparent high polymersthat may be included in the insulating substrate 120 includetriacetylcellulose (TAC), polycarbonate (PC), polyethersulfone (PES),polyethyleneterephthalate (PET), polyethylenenaphthalate (PEN),polyvinylalcohol (PVA), polymethylmethacrylate (PMMA), cyclo-olefinpolymer (COP), and combinations thereof.

The insulating substrate 120 may be optically isotropic. Alternatively,the insulating substrate 120 may be optically anisotropic.

The gate line 131 is disposed on the insulating substrate 120. The gateline 131 includes a gate barrier layer 131 a, a gate conductive layer131 b, and a gate copper nitride layer 131 c.

The gate barrier layer 131 a is disposed on the insulating substrate120. The gate barrier layer 131 a increases the adhesive strengthbetween the gate line 131 and the insulating substrate 120. Examples ofbarrier material that may be used in the gate barrier layer 131 ainclude molybdenum (Mo), molybdenum-titanium (Mo—Ti) alloy,molybdenum-tungsten (Mo—W) alloy, molybdenum-chromium (Mo—Cr) alloy,molybdenum-niobium (Ni) alloy, and combinations thereof.

Copper nitride may be disposed on a side surface of the gate barrierlayer 131 a.

The gate conductive layer 131 b is disposed on the gate barrier layer131 a. The gate conductive layer 131 b may include copper or copperalloy. When the gate conductive layer 131 b includes copper, theresistance of the gate conductive layer 131 b is about 2.1 μΩcm to about2.3 μΩcm. Thus, the resistance of the gate conductive layer 131 b isabout 30% smaller than that of an aluminum layer, which has a resistanceof about 3.1 μΩcm. In addition, the gate conductive layer 131 b haslower electro-migration than an aluminum layer.

The gate copper nitride layer 131 c is disposed on an upper surface anda side surface of the gate conductive layer 131 b. The gate coppernitride layer 131 c includes copper nitride. Nitride plasma may beimplanted into a copper line to form the gate copper nitride layer 131c. Examples of nitride plasma that may be implanted into the copper lineinclude ammonia (NH₃) plasma, nitrogen (N₂) plasma, and combinationsthereof.

The gate copper nitride layer 131 c prevents the copper of the gateconductive layer 131 b from mixing with impurities such as oxygen andsilicon. In addition, the gate copper nitride layer 131 c has greaterresistance to etching than the gate conductive layer 131 b andtherefore, may protect the gate conductive layer 131 b from a subsequentprocess, such as an etching process or a stripping process.

A gate electrode 118 of the thin film transistor 155 is disposed on theinsulating substrate 120. The gate electrode 118 may include copper orcopper alloy. The gate electrode 118 may be formed on substantially thesame layer as the gate line 131. The gate electrode 118 includes a gatebarrier pattern 118 a, a gate conductive pattern 118 b, and a gatecopper nitride pattern 118 c.

The gate barrier pattern 118 a is disposed on the insulating substrate120. The gate barrier pattern 118 a may include molybdenum (Mo),molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy,molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni) alloy, andcombinations thereof. For example, the gate barrier pattern 118 a mayinclude substantially the same material as the gate barrier layer 131 aof the gate line 131.

The gate conductive pattern 118 b is disposed on the gate barrierpattern 118 a. The gate conductive pattern 118 b may include copper orcopper alloy. For example, the gate conductive pattern 118 b may includesubstantially the same material as the gate conductive layer 131 b ofthe gate line 131.

The gate copper nitride pattern 118 c is disposed on an upper surfaceand a side surface of the gate conductive pattern 118 b. The coppernitride pattern 118 c may include copper nitride. For example, the gatecopper nitride pattern 118 c may include substantially the same materialas the gate copper nitride layer 131 c of the gate line 131.

The gate insulating layer 126 is disposed on the insulating substrate120 to cover the gate line 131 and the gate electrode 118.

Referring to FIG. 3, the gate insulating layer 126 includes a first gateinsulating layer 126 a, a second gate insulating layer 126 b, and athird gate insulating layer 126 c. The gate insulating layer 126 may beformed through a chemical vapor deposition (CVD) method using silane gasand nitride mixture gas. The chemical vapor deposition method may be aplasma enhanced chemical vapor deposition (PECVD) method. The nitridemixture gas may contain nitrogen (N₂) gas, ammonia (NH₃) gas, andcombinations thereof.

The first gate insulating layer 126 a is disposed on the insulatingsubstrate 120 on which the gate line 131 and the gate electrode 118 areformed. The first gate insulating layer 126 a may include a low densitysilicon nitride and the density of the first gate insulating layer 126 amay be low. The amount of silane gas in the first gas mixture may be nomore than about 6.43% by volume. Silicon atoms may be securely combinedwith nitrogen atoms in the low density silicon nitride. For example, thenumber of dangling bonds on which electrons may be trapped may bedecreased in the low density silicon nitride, which may decrease thedeposition speed. In addition, the surface structure of the low densitysilicon nitride may be dense making it a good electrical insulator.

The second gate insulating layer 126 b is disposed on the first gateinsulating layer 126 a and may include a high density silicon nitride.The density of the second gate insulating layer 126 b may be higher thanthat of the first gate insulating layer 126 a. The amount of silane gasin the second gas mixture may be no less than about 6.43% by volume. Thesecond gas mixture may contain more silane gas than the first gasmixture. Silicon atoms may be loosely combined with nitrogen atoms inthe high density silicon nitride. For example, the number of danglingbonds may be increased in the high density silicon nitride such thatelectrons may be trapped in the dangling bonds. The deposition speed ofthe high density silicon nitride may be faster than that of low densitysilicon nitride. In addition, the surface structure of the low densitysilicon nitride may be loose and the high density silicon nitride may bea poorer electrical insulator than the low density silicon nitride.

The third gate insulating layer 126 c is disposed on the second gateinsulating layer 126 b and may include substantially the same lowdensity silicon nitride as the first gate insulating layer 126 a. Sincethe third gate insulating layer 126 c includes substantially the samematerial as the first gate insulating layer 126 a, any furtherexplanation concerning the above elements will be omitted. When thethird gate insulating layer 126 c includes low density silicon nitride,the electrical characteristics of the amorphous silicon pattern 137 a ofthe semiconductor pattern 137 may be improved.

The nitrogen density of the first gate insulating layer 126 a may behigher than that of the second gate insulating layer 126 b so thatcopper atoms in the gate line 131 and the gate electrode 118 may not becombined with silicon atoms. The deposition speed of the second gateinsulating layer 126 b may be faster than that of the first gateinsulating layer 126 b, thereby decreasing the manufacturing time of thearray substrate. The third gate insulating layer 126 c may have a denserstructure and therefore, more secure electrical characteristics, thanthe second gate insulating layer 126 b. Thus, the third gate insulatinglayer 126 c may improve the electrical characteristics of the amorphoussilicon pattern 137 a.

Referring again to FIG. 1, FIG. 2, and FIG. 4, the semiconductor pattern137 of the thin film transistor 155 is disposed on the gate insulatinglayer 126 corresponding to the gate electrode 118. The semiconductorpattern 137 includes the amorphous silicon pattern 137 a and an n+amorphous silicon pattern 137 b.

The amorphous silicon pattern 137 a is disposed on the gate insulatinglayer 126 corresponding to the gate electrode 118. The amorphous siliconpattern 137 a may include a lower amorphous silicon pattern (not shown)and an upper amorphous silicon pattern (not shown). The lower amorphoussilicon pattern may be deposited at a higher temperature and at a slowerspeed than the upper amorphous silicon pattern such that it has a denserstructure than the upper amorphous silicon pattern.

When an electric field is applied between the gate electrode 118 and thesource electrode 117, a channel is formed in the lower amorphous siliconpattern adjacent to the gate insulating layer 126. In FIG. 1, FIG. 2,FIG. 3, and FIG. 4, the lower amorphous silicon pattern has a denserstructure than the upper amorphous silicon pattern and therefore, thenumber of the dangling bonds trapping electrons is smaller in the loweramorphous silicon pattern. Thus, the electrical characteristics of thesemiconductor pattern 137 may be improved. In addition, the depositionspeed of the upper amorphous silicon pattern may be faster than that ofthe lower amorphous silicon pattern, which may decrease themanufacturing time.

The n+ amorphous silicon pattern 137 b includes a first pattern and asecond pattern. The first and second patterns are spaced apart from eachother on the amorphous silicon pattern 137 a.

The data line 133 is disposed on the gate insulating layer 126. The dataline 133 includes a data barrier layer 133 a, a data conductive layer133 b, and a data copper nitride layer 133 c.

The data barrier layer 133 a is on the gate insulating layer 126, theamorphous silicon pattern 137 a, and the n+ amorphous silicon pattern137 b. The data barrier layer 133 a prevents the silicon atoms of thegate insulating layer 126 from diffusing into the data conductive layer133 b, which may prevent the resistance of the data conductive layer 133b from increasing. Examples of a conductive material that may beincluded in the data barrier layer 133 a include molybdenum (Mo),molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy,molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Mo—Nb) alloy, andcombinations thereof. A metal nitride layer may be formed on a sidesurface of the data barrier layer 133 a.

The data conductive layer 133 b is disposed on the data barrier layer133 a. The data conductive layer 133 b may include copper or copperalloy. For example, the data conductive layer 133 b may includesubstantially the same material as the gate conductive layer 131 b.Thus, any further explanation concerning the above elements will beomitted.

The data copper nitride layer 133 c is disposed on an upper surface anda side surface of the data conductive layer 133 b. The data coppernitride layer 133 c may include substantially the same copper nitride asthe gate copper nitride layer 131 c. Alternatively, a data copperhydrogenated layer may be formed on the upper surface and the sidesurface of the data conductive layer 133 b.

A source electrode 117 of the thin film transistor 155 is disposed on afirst pattern of the n+ amorphous silicon pattern. The source electrode117 may include copper or copper alloy. The source electrode 117 may beformed on substantially the same layer as the data line 133. The sourceelectrode 117 is connected to the data line 133 and includes a sourcebarrier pattern 117 a, a source conductive pattern 117 b, and a sourcecopper nitride pattern 117 c.

The source barrier pattern 117 a is disposed on the first pattern of then+ amorphous silicon pattern. The source barrier pattern 117 a mayinclude a conductive material such as molybdenum (Mo),molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy,molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni) alloy, andcombinations thereof. For example, the source barrier pattern 117 a mayinclude substantially the same material as the data barrier layer 133 aof the data line 133.

The source conductive pattern 117 b is disposed on the source barrierpattern 117 a. The source conductive pattern 117 b may include copper orcopper alloy. For example, the source conductive pattern 117 b mayinclude substantially the same material as the data conductive layer 133b of the data line 133.

The source copper nitride pattern 117 c is disposed on an upper surfaceand a side surface of the source conductive pattern 117 b. The sourcecopper nitride pattern 117 c may include copper nitride. For example,the source copper nitride pattern 117 c may include substantially thesame material as the data copper nitride layer 133 c of the data line133.

A drain electrode 119 of the thin film transistor 155 is disposed on asecond pattern of the n+ amorphous silicon pattern. The drain electrode119 may include copper or a copper alloy. For example, the drainelectrode 119 may be formed from substantially the same layer as thedata line 133. The drain electrode 119 is electrically connected to thepixel electrode 112 and includes a drain barrier pattern 119 a, a drainconductive pattern 119 b, and a drain copper nitride pattern 119 c.

The drain barrier pattern 119 a is on the second pattern of the n+amorphous silicon pattern. The drain barrier pattern 119 a may includemolybdenum (Mo), molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten(Mo—W) alloy, molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni)alloy, and combinations thereof. For example, the drain barrier pattern119 a may include substantially the same material as the data barrierlayer 133 a of the data line 133.

The drain conductive pattern 119 b is disposed on the drain barrierpattern 119 a. The drain conductive pattern 119 b may include copper ora copper alloy. For example, the drain conductive pattern 119 b mayinclude substantially the same material as the data conductive layer 133b of the data line 133.

The drain copper nitride pattern 119 c is disposed on an upper surfaceand a side surface of the drain conductive pattern 119 b. The draincopper nitride pattern 119 c may include copper nitride. For example,the drain copper nitride pattern 119 c may include substantially thesame material as the data copper nitride layer 133 c of the data line133.

The passivation layer 116 is disposed on the gate insulating layer 126to cover the semiconductor pattern 137, the data line 133, the sourceelectrode 117, and the drain electrode 119. The passivation layer 116may include silicon nitride. Alternatively, the passivation layer 116may have a double layered structure including a low density siliconnitride layer and a high density silicon nitride layer. The passivationlayer 116 may have a contact hole 151 through which the drain electrode119 is partially exposed.

The pixel electrode 112 is disposed on the passivation layer 116 and isconnected to the drain electrode 119 through the contact hole 151. Thepixel electrode 112 may include a transparent conductive material.Examples of the transparent conductive material that may be included inthe pixel electrode 112 include indium tin oxide (ITO), indium zincoxide (IZO), amorphous indium tin oxide (a-ITO), and combinationsthereof.

According to the array substrate shown in FIG. 1, FIG. 2, FIG. 3, andFIG. 4, the gate line 131, the gate electrode 118, the data line 133,the source electrode 117, and the drain electrode 119 include the gatecopper nitride line 131 c, the gate copper nitride pattern 118 c, thedata copper nitride line 133 c, the source copper nitride pattern 117 c,and the drain copper nitride pattern 119 c, respectively, to decreasethe occurrence of defects of the gate line 131, the gate electrode 118,the data line 133, the source electrode 117 and the drain electrode 119.In addition, the gate insulating layer 126 may have a triple layeredstructure, which may decrease the manufacturing time of the arraysubstrate and improve the electrical characteristics of the amorphoussilicon pattern 137 a of the array substrate.

FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12, FIG.13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, and FIG. 19 arecross-sectional views showing a method of manufacturing the arraysubstrate shown in FIG. 1.

Referring to FIG. 1 and FIG. 5, a primary gate barrier layer 141 and aprimary gate conductive layer 142 are formed on the insulating substrate120, in sequence. A copper nitride layer (not shown) may be formed onthe primary gate conductive layer 142 through a sputtering process. Agate photoresist film 143 is coated on the primary gate conductive layer142.

The gate photoresist film 143 is exposed through a gate mask 171. Thegate mask 171 includes a light blocking portion 171 a and a transparentportion 171 b. The light blocking portion 171 a corresponds to the gateline 131 and the gate electrode 118.

Referring to FIG. 1 and FIG. 6, the exposed gate photoresist film 143 isdeveloped to form a gate photoresist pattern 143 a on the primary gateconductive layer 142.

Referring to FIG. 1 and FIG. 7, the primary gate conductive layer 142and the primary gate barrier layer 141 are partially etched, using thegate photoresist pattern 143 a as an etching mask, to form the gatebarrier layer 131 a, a primary gate conductive layer 131 d, the gatebarrier pattern 118 a, and a primary gate conductive pattern 118 d onthe insulating substrate 120. The gate photoresist pattern 143 a is thenremoved from the primary gate conductive layer 131 d and the primarygate conductive pattern 118 c.

Referring to FIG. 1 and FIG. 8, nitride plasma is applied to theinsulating substrate 120, on which the primary gate conductive layer 131d, the gate barrier layer 131 a, the gate barrier pattern 118 a, and theprimary gate conductive pattern 118 d are formed. For example, ammoniagas and nitrogen gas may be injected into a chamber (not shown) and anelectric power of no less than about 300 W may be applied to the ammoniagas and the nitrogen gas for a period of no less than about 20 seconds.

Referring to FIG. 1 and FIG. 9, the nitride plasma 188 a (shown in FIG.8) is injected onto an upper surface and a side surface of the primarygate conductive layer 131 d to form the gate conductive layer 131 b andthe gate copper nitride layer 131 c on the gate barrier layer 131 a. Inaddition, the nitride plasma 188 a is also injected onto an uppersurface and a lower surface of the primary gate conductive pattern 118 dto form the gate conductive pattern 118 b and the gate copper nitridepattern 118 c on the gate barrier pattern 118 a.

Furthermore, copper oxide that may be formed on surfaces of the primarygate conductive layer 131 d and the primary gate conductive pattern 118d by oxygen or water vapor is converted into copper nitride by thenitride plasma 118 a. Copper nitride has better electrical andmanufacturing characteristics than copper oxide. For example, coppernitride has less resistance and greater mechanical strength than copperoxide.

A gas mixture, including silane gas and a nitride mixture gas, may beinjected onto the insulating substrate 120, on which the gate electrode118, the gate line 131, and the gate insulating layer 126 (shown in FIG.2) are formed, through a chemical vapor deposition (CVD) method.Examples of the nitride mixture gas that may be injected onto theinsulating substrate 120 include nitrogen gas, ammonia gas, andcombinations thereof. The chemical vapor deposition method may be aplasma enhanced chemical vapor deposition (PECVD) method.

FIG. 10, FIG. 11, FIG. 12, and FIG. 13 are cross-sectional views showinga method of disposing the gate insulating layer shown in FIG. 2.

Referring to FIG. 9 and FIG. 10, the first gas mixture is injected intothe chamber. The amount of silane gas in the first gas mixture may be nomore than about 6.43% by volume. An electric power is applied to thefirst gas mixture to generate a low density silicon nitride plasma 189a, which is applied to the insulating substrate 120 on which the gateelectrode 118 and the gate line 131 are formed. Thus, the first gateinsulating layer 126 a (shown in FIG. 3), including low density siliconnitride, is formed on the insulating substrate 120 on which the gateelectrode 118 and the gate line 131 are formed. For example, the gateinsulating layer 126 may be formed in the chamber in which the nitrideplasma is applied to the insulating substrate 120, in situ.

When the amount of silane gas in the first gas mixture for forming thefirst gate insulating layer 126 a is no more than about 6.43% by volume,enough nitrogen atoms may be present for the silicon atoms in the silanegas to react with the nitrogen atoms, thereby forming silicon nitride.Thus, the first gate insulating layer 126 a may have a dense structureand be a good electrical insulator. However, the deposition speed of thefirst gate insulating layer 126 a may be decreased.

When the amount of silane gas in the first gas mixture for disposing thefirst gate insulating layer 126 a is more than about 6.43% by volume, aportion of the silicon atoms in the silane gas may not react withnitrogen atoms and therefore, the silicon atoms may react with copperatoms of the gate line 131 and the gate electrode 118, forming siliconcopper (CuSi). Silicon atoms of the silicon copper may be separated fromthe copper atoms of the silicon copper and may be implanted into thegate line 131 and the gate electrode 118. When the silicon atoms areimplanted into the gate line 131 and the gate electrode 118, theresistance of the gate line 131 and the gate electrode 118 may begreatly increased. However, in FIG. 9 and FIG. 10, the amount of silanegas in the first gas mixture for forming the first gate insulating layer126 a is no more than about 6.43% by volume and therefore, the coppernitride of the gate copper nitride layer 131 c and the gate coppernitride pattern 118 c may not react with the silicon atoms.

In FIG. 9 and FIG. 10, the amount of silane gas in the first gas mixturefor forming the first gate insulating layer 126 a is about 2.24% byvolume and the electric power applied to the chamber is about 900 W. Inaddition, the thickness of the first gate insulating layer 126 a is noless than about 10 Å.

Referring to FIG. 9 and FIG. 11, the second gas mixture for forming thesecond gate insulating layer 126 b (shown in FIG. 3) is injected intothe chamber. The amount of silane gas in the second gas mixture is noless than about 6.43% by volume. An electric power is applied to thesecond gas mixture to generate high density silicon nitride plasma 189b, and the high density silicon nitride plasma 189 b is applied to thefirst gate insulating layer 126 a. Thus, the second gate insulatinglayer 126 b (shown in FIG. 3), including high density silicon nitride,is disposed on the first gate insulating layer 126 a. For example, thefirst gate insulating layer 126 a and the second gate insulating layer126 b may be formed in the chamber, in situ.

When the amount of silane gas in the second gas mixture for disposingthe second gate insulating layer 126 b is no less than about 6.43% byvolume, the silicon atoms in the silane gas may not sufficiently reactwith the nitrogen atoms in the nitride mixture gas. Thus, the secondgate insulating layer 126 b may have a loose structure and theinsulating characteristics of the second gate insulating layer 126 b maybe poorer than that of the first gate insulating layer 126 a such thatthe second gate insulating layer 126 b has a smaller electricalresistance than the first gate insulating layer 126 a. However, thedeposition speed of the second gate insulating layer 126 b may be fasterthan that of the first gate insulating layer 126 a.

In FIG. 9 and FIG. 11, the first gate insulating layer 126 a may blockthe silicon atoms to protect the gate electrode 118 and the gate line131, even though the amount of the silane gas in the second gas mixturefor forming the second gate insulating layer 126 b may be no less thanabout 6.43% by volume. Thus, the silicon atoms may not be implanted intothe gate line 131 and the gate electrode 118.

For example, the amount of silane gas in the second gas mixture forforming the second gate insulating layer 126 b may be about 6.43% byvolume and the electric power applied to the chamber may be about 1200W.

Referring to FIG. 9 and FIG. 12, the third gas mixture for forming thethird gate insulating layer 126 c (shown in FIG. 3) is injected into thechamber. The amount of silane gas in the third gas mixture is no morethan about 6.43% by volume. Electric power is applied to the third gasmixture to generate a low density silicon nitride plasma 189 c, which isapplied to the second gate insulating layer 126 b. Thus, the third gateinsulating layer 126 c, including low density silicon nitride, is formedon the second gate insulating layer 126 b.

When the amount of silane gas in the third gas mixture for forming thethird gate insulating layer 126 c is no more than about 6.43% by volume,the third gate insulating layer 126 c may have a dense structure and maybe a good electrical insulator. However, the deposition speed of thethird gate insulating layer 126 c may be decreased.

In FIG. 9 and FIG. 12, the amount of the silane gas in the third gasmixture for forming the third gate insulating layer 126 c may be about2.24% by volume and the electric power applied to the chamber may beabout 900 W.

Referring to FIG. 13 and FIG. 14, the gate insulating layer 126,including the first gate insulating layer 126 a, the second gateinsulating layer 126 b, and the third gate insulating layer 126 c, isformed on the insulating substrate 120 on which the gate electrode 118and the gate line 131 are formed.

Referring to FIG. 15, a lower amorphous silicon layer (not shown) and anupper amorphous silicon layer (not shown) are deposited on the gateinsulating layer 126, in sequence. The upper amorphous silicon layer mayhave a looser structure than the lower amorphous silicon layer.

The lower amorphous silicon layer may be deposited at a low electricpower and at a decreased speed so that the lower amorphous silicon layermay have a dense structure and good electrical characteristics. Theupper amorphous silicon layer may be deposited at a high electric powerand at an increased speed so that the upper amorphous silicon layer mayhave a loose structure. For example, the lower amorphous silicon layermay be formed at an electric power of about 150 W and the upperamorphous silicon layer may be formed at an electric power of about 300W. The amorphous silicon layer is deposited on the gate insulating layer126 and includes the lower amorphous silicon layer and the upperamorphous silicon layer.

Then, n+ impurities are implanted into an upper portion of the amorphoussilicon layer to form an n+ amorphous silicon layer (not shown).

The n+ amorphous silicon layer and the amorphous silicon layer arepartially etched to form a primary n+ amorphous silicon pattern 137 cand the amorphous silicon pattern 137 a.

Referring to FIG. 16, a primary data barrier layer (not shown) and aprimary data conductive layer (not shown) are formed on the gateinsulating layer 126, in sequence. The gate insulating layer 126includes the primary n+ amorphous silicon pattern 137 c and theamorphous silicon pattern 137 a. Alternatively, a copper nitride layer(not shown) may be deposited on the primary data conductive layerthrough a sputtering process. A data photoresist film (not shown) isformed on the primary data conductive layer.

The primary data barrier layer and the primary data conductive layer arepartially etched through a photolithography process using a data mask(not shown) to form the data barrier layer 133 a, a primary dataconductive layer 133 d, the source barrier pattern 117 a, a primarysource conductive pattern 117 d, the drain barrier pattern 119 a, and aprimary drain conductive pattern 119 d.

The nitride plasma 188 b is implanted onto the gate insulating layer 126including the primary n+ amorphous silicon pattern 137 c, the amorphoussilicon pattern 137 a, the data barrier layer 133 a, a primary dataconductive layer 133 d, the source barrier pattern 117 a, a primarysource conductive pattern 117 d, the drain barrier pattern 119 a, and aprimary drain conductive pattern 119 d.

Referring to FIG. 16 and FIG. 17, the nitride plasma 188 b is implantedonto upper and side surfaces of the primary data conductive layer 133 d,the primary source conductive pattern 117 d, and the primary drainconductive pattern 119 d to form the data conductive layer 133 b, thedata copper nitride layer 133 c, the source conductive pattern 117 b,the source copper nitride pattern 117 c, the drain conductive pattern119 b, and the drain copper nitride pattern 119 c. For example, ammoniagas and nitrogen gas may be injected into a chamber (not shown), and anelectric power of about 300 W may be applied to the ammonia gas and thenitrogen gas for more than about 20 seconds.

Referring to FIG. 17, the primary n+ amorphous silicon pattern 137 c(shown in FIG. 16) interposed between the source electrode 117 and thedrain electrode 119 is partially etched, using the source electrode 117and the drain electrode 119 as an etching mask, to form thesemiconductor pattern 137 including the n+ amorphous silicon pattern 137b and the amorphous silicon pattern 137 a.

The data copper nitride layer 133 c, the source copper nitride pattern117 c, and the drain copper nitride pattern 119 c may protect the dataline 133, the source electrode 117, and the drain electrode 119,respectively, from the etchant for etching the primary n+ amorphoussilicon pattern 137 c.

In FIG. 15, FIG. 16, and FIG. 17, the semiconductor pattern 137, thedata line 133, the source electrode 117, and the drain electrode 119 areformed using two photo masks. Alternatively, the semiconductor pattern,the data line, the source electrode, and the drain electrode may beformed using one photo mask.

Referring to FIG. 18, the passivation layer 116 is formed on the gateinsulating layer 126 to cover the semiconductor pattern 137, the dataline 133, the source electrode 117, and the drain electrode 119. Forexample, silane gas and the nitride mixture gas may be injected onto thegate insulating layer 126, and the passivation layer 116 may be formedon the gate insulating layer 126 by a chemical vapor deposition (CVD)method.

As shown in FIG. 18, the passivation layer 116 may include a firstpassivation layer (not shown) and a second passivation layer (notshown). The second passivation layer may be disposed on the firstpassivation layer.

The first passivation layer may include low density silicon nitride. Themethod for forming the low density silicon nitride of the firstpassivation layer is substantially the same as that described withrespect to FIG. 10. Thus, any further explanation concerning the aboveelements will be omitted.

The second passivation layer may include high density silicon nitride.The method for forming the high density silicon nitride of the secondpassivation layer is substantially the same as that described withrespect to FIG. 11. Thus, any further explanation concerning the aboveelements will be omitted.

In FIG. 18, the passivation layer 116 has a double layered structureincluding first and second passivation layers. Alternatively, thepassivation layer may have a single layered structure or a multi-layeredstructure including no less than three layers.

Referring to FIG. 19, the passivation layer 116 may be partially etchedto form the contact hole 151 through which the drain electrode 119 ispartially exposed. Alternatively, a laser beam may be irradiated ontothe pixel electrode 112 corresponding to the drain electrode 119 to formthe contact hole 151 after the pixel electrode 112 is formed.

The pixel electrode 112 connected to the drain electrode 119 is formedon the passivation layer 116 and the contact hole 151 is formed in thepassivation layer 116.

According to the method of manufacturing the display substrate of FIG.4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, FIG. 12,FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17, FIG. 18, and FIG. 19, anadditional protective layer for protecting an upper portion of the gateline 131, the gate electrode 118, the data line 133, the sourceelectrode 117, and the drain electrode 119 may be omitted, therebydecreasing manufacturing time of the display substrate.

In addition, the copper nitride layer may cover the side surface of thedata line 133, the source electrode 117, and the drain electrode 119 toprevent the data line 133, the source electrode 117, and the drainelectrode 119 from the etchant for etching the primary n+ amorphoussilicon pattern 137 c.

Example I

A primary gate conductive pattern 188 d (shown in FIG. 8) was treated bynitride plasma or hydrogen plasma. A gate insulating layer having amultilayered structure and including a low density silicon nitride layerand a high density silicon nitride layer was deposited on the substrate.The nitride plasma or the hydrogen plasma was generated by an electricpower of about 600 W during about 20 seconds. An electric power of about900 W was applied to a gas mixture including silane gas and a nitridemixture gas and the amount of silane gas in the gas mixture was about2.24% by volume. An electric power of about 1200 W was applied to a gasmixture including silane gas and a nitride mixture gas and the amount ofthe silane gas in the gas mixture was about 6.43% by volume.

When a first low density silicon nitride layer, a high density siliconnitride layer, and a second low density silicon nitride layer wereformed after the nitride plasma treatment, the resistance of the gateline was about 2.1 μΩcm to 2.3 μΩcm.

When a first low density silicon nitride layer, a high density siliconnitride layer, and a second low density silicon nitride layer wereformed after the hydrogen plasma treatment, the resistance of the gateline was about 2.5 μΩcm to 2.8 μΩcm.

When a high density silicon nitride layer and a low density siliconnitride layer were formed after the nitride plasma treatment, theresistance of the gate line was about 2.9 μΩcm to 3.0 μΩcm.

When a high density silicon nitride layer and a low density siliconnitride layer were formed after the hydrogen plasma treatment, theresistance of the gate line was about 3.0 μΩcm to 3.1 μΩcm.

Therefore, when the first low density silicon nitride layer, the highdensity silicon nitride layer, and the second low density siliconnitride layer were formed, in sequence, after the nitride plasmatreatment, the resistance of the gate line was minimized.

FIG. 20 is a cross-sectional view showing a display device in accordancewith another exemplary embodiment of the present invention.

Referring to FIG. 20, the display device includes an array substrate180, an opposite substrate 170, and a liquid crystal layer 108. Thearray substrate 180 of FIG. 20 is the same as that of FIG. 1, FIG. 2,FIG. 3, and FIG. 4. Thus, the same reference numerals will be used torefer to the same or like parts and any further explanation concerningthe above elements will be omitted.

The opposite substrate 170 includes an opposite insulating substrate100, a black matrix 102 b, a color filter 104, and a common electrode106. The opposite substrate 170 may further include a plurality of colorfilters.

The opposite insulating substrate 100 includes a transparent insulatingmaterial. Examples of the transparent insulating material that may beincluded in the opposite insulating substrate 100 include glass, quartz,and synthetic resin. For example, the opposite insulating substrate 100may include a transparent synthetic resin.

The black matrix 102 is on the opposite insulating substrate 100 toblock light that is incident in a region in which liquid crystals areincontrollable. Thus, it may be possible to improve the contrast ratioof the display device.

The color filter 104 is on the opposite insulating substrate 100, onwhich the black matrix 102 is formed, to transmit color light having awavelength corresponding to a color. The color filter 104 corresponds toa pixel electrode 112 of the array substrate 180.

The common electrode 106 is on the opposite insulating substrate 100 onwhich the black matrix 102 and the color filter 104 are formed. Thecommon electrode 106 includes a transparent conductive material.Examples of the transparent conductive material include indium tin oxide(ITO), indium zinc oxide (IZO), amorphous indium tin oxide (a-ITO), andcombinations thereof.

A spacer (not shown) may be interposed between the array substrate 180and the opposite substrate 170 to maintain a distance between the arraysubstrate 180 and the opposite substrate 170. The spacer may be a beadspacer, a ball spacer, or a column spacer.

A liquid crystal layer 108 is interposed between the array substrate 180and the opposite substrate 170. When a voltage difference occurs betweenthe common electrode 106 and the pixel electrode 112, an electric fieldis formed between the common electrode 106 and the pixel electrode 112.The orientations of the liquid crystals of the liquid crystal layer 108vary in response to the electric field formed between the commonelectrode 106 and the pixel electrode 112. Thus, light transmittance ofthe liquid crystal layer 108 is changed and an image having a gray-scaleis displayed.

A sealant (not shown) may seal the liquid crystal layer 108 between thearray substrate 180 and the opposite substrate 170.

Accordingly, the occurrence of defects in the array substrate 180 of thedisplay device of FIG. 20 may be decreased and the manufacturing processof the array substrate 180 may be simplified. Thus, the image displayquality of the display device may be improved and the manufacturing costof the display device may be decreased.

FIG. 21 is a cross-sectional view showing an array substrate inaccordance with another embodiment of the present invention. The arraysubstrate of FIG. 21 is substantially the same as that of FIG. 1, FIG.2, FIG. 3, and FIG. 4, except for the gate line, the gate electrode, thedata line, the source electrode, and the drain electrode. Thus, the samereference numerals will be used to refer to the same or like parts andany further explanation concerning the above elements will be omitted.

Referring to FIG. 21, the gate line 1131 is disposed on an insulatingsubstrate 120 and includes a gate barrier layer 1131 a, a gateconductive layer 1131 b, and a gate copper nitride layer 1131 c.

The gate barrier layer 1131 a is disposed on the insulating substrate120. The gate barrier layer 1131 a may include molybdenum (Mo),molybdenum-titanium (Mo—Ti) alloy, molybdenum-tungsten (Mo—W) alloy,molybdenum-chromium (Mo—Cr) alloy, molybdenum-niobium (Ni) alloy, andcombinations thereof. The gate barrier layer 1131 a may increase theadhesive strength between the gate line 1131 and the insulatingsubstrate 120.

The gate conductive layer 1131 b is disposed on the gate barrier layer1131 a. The gate conductive layer 1131 b may include copper or copperalloy.

The gate copper nitride layer 1131 c is disposed on an upper surface ofthe gate conductive layer 1131 b. The gate copper nitride layer 1131 cmay prevent copper of the gate conductive layer 1131 b from beingcombined with silicon of the gate insulating layer 126. The gate coppernitride layer 1131 c may include copper nitride. For example, the gatecopper nitride layer 1131 c may be formed through a copper sputteringprocess in a nitrogen atmosphere.

The gate electrode 1118 of the thin film transistor 1155 is on theinsulating substrate 120. The gate electrode 1118 is formed onsubstantially the same layer as the gate line 1131 and includes a gatebarrier pattern 1118 a, a gate conductive pattern 1118 b, and a gatecopper nitride pattern 1118 c.

The gate barrier pattern 1118 a is disposed on the insulating substrate120. The gate barrier pattern 1118 a may include substantially the samematerial as the gate barrier layer 1131 a of the gate line 1131.

The gate conductive pattern 1118 b is disposed on the gate barrierpattern 1118 a. The gate conductive pattern 1118 b may include copper orcopper alloy. For example, the gate conductive pattern 1118 b mayinclude substantially the same material as the gate conductive layer1131 b of the gate line 1131.

The gate copper nitride pattern 1118 c is disposed on an upper surfaceof the gate conductive pattern 1118 b. The gate copper nitride pattern1118 c may include copper nitride. For example, the gate copper nitridepattern 1118 c may include substantially the same material as the gatecopper nitride layer 1131 c of the gate line 1131.

The data line 1133 is disposed on the gate insulating layer 126. Thedata line 1133 includes a data barrier layer 1133 a, a data conductivelayer 1133 b, and a data copper nitride layer 1133 c.

The data barrier layer 1133 a is disposed on the gate insulating layer126, an amorphous silicon pattern 137 a, and an n+ amorphous siliconpattern 137 b. The data barrier layer 1133 a prevents the silicon atomsof the gate insulating layer 126 from diffusing into the data conductivelayer 1133 b.

The data conductive layer 1133 b is disposed on the data barrier layer1133 a. The data conductive layer 1133 b may include copper or copperalloy. For example, the data conductive layer 1133 b may includesubstantially the same material as the gate conductive layer 1131 b.Thus, any further explanation concerning the above elements will beomitted.

The data copper nitride layer 1133 c is formed on an upper surface ofthe data conductive layer 1133 b. The data copper nitride layer 1133 cmay include copper nitride. For example, the data copper nitride layer1133 c may include substantially the same copper nitride as the gatecopper nitride layer 1131 c.

A source electrode 1117 of the thin film transistor 1155 is on a firstpattern of the n+ amorphous silicon pattern. The source electrode 1117may include copper or copper alloy. For example, the source electrode1117 may be formed on substantially the same layer as the data line1133. The source electrode 1117 is connected to the data line 1133 andincludes a source barrier pattern 1117 a, a source conductive pattern1117 b, and a source copper nitride pattern 1117 c.

The source barrier pattern 1117 a is on the first pattern of the n+amorphous silicon pattern. The source barrier pattern 1117 a may includesubstantially the same material as the data barrier layer 1133 a of thedata line 1133.

The source conductive pattern 1117 b is disposed on the source barrierpattern 1117 a. The source conductive pattern 1117 b may include copperor copper alloy. For example, the source conductive pattern 1117 b mayinclude substantially the same material as the data conductive layer1133 b of the data line 1133.

The source copper nitride pattern 1117 c is disposed on an upper surfaceof the source conductive pattern 1117 b. The source copper nitridepattern 1117 c may include copper nitride. For example, the sourcecopper nitride pattern 1117 c may include substantially the samematerial as the data copper nitride layer 1133 c of the data line 1133.

A drain electrode 1119 of the thin film transistor 1155 is disposed on asecond pattern of the n+ amorphous silicon pattern. The drain electrode1119 is formed on substantially the same layer as the data line 1133.The drain electrode 1119 is connected to the pixel electrode 1112 andincludes a drain barrier pattern 1119 a, a drain conductive pattern 1119b, and a drain copper nitride pattern 1119 c.

The drain barrier pattern 1119 a is disposed on the second pattern ofthe n+ amorphous silicon pattern. The drain barrier pattern 1119 a mayinclude substantially the same material as the data barrier layer 1133 aof the data line 1133.

The drain conductive pattern 1119 b is disposed on the drain barrierpattern 1119 a. The drain conductive pattern 1119 b may include copperor copper alloy. For example, the drain conductive pattern 1119 b mayinclude substantially the same material as the data conductive layer1133 b of the data line 1133.

The drain copper nitride pattern 1119 c is disposed on an upper surfaceof the drain conductive pattern 1119 band may include copper nitride.For example, the drain copper nitride pattern 1119 c may includesubstantially the same material as the data copper nitride layer 1133 cof the data line 1133.

FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26 are cross-sectionalviews showing a method of manufacturing the array substrate shown inFIG. 21. The method of FIG. 22, FIG. 23, FIG. 24, FIG. 25, and FIG. 26is substantially the same as in FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9,FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14, FIG. 15, FIG. 16, FIG. 17,FIG. 18, and FIG. 19, except with regard to the processes for formingthe gate line, the gate electrode, the data line, the source electrode,and the drain electrode. Thus, the same reference numerals will be usedto refer to the same or like parts and any further explanationconcerning the above elements will be omitted.

Referring to FIG. 21 and FIG. 22, a primary gate barrier layer 1141 anda primary gate conductive layer 1142 are formed on the insulatingsubstrate 120, in sequence. A primary copper nitride layer 1144 isdeposited on the primary gate conductive layer 1142 through a sputteringprocess. A gate photoresist film 1143 is coated on the primary gatecopper nitride layer 1144.

The gate photoresist film 1143 is exposed to ultraviolet light through agate mask 1171. The gate mask 1171 includes a light blocking portion1171 a and a transparent portion 1171 b. The light blocking portion 1171blocks a portion of the ultraviolet light and the remaining portion ofthe ultraviolet light passes through the transparent portion 1171 b. Thelight blocking portion 1171 a corresponds to the gate line 1131 and thegate electrode 1118 and the transparent portion 1171 b corresponds tothe remainder of the array substrate.

Referring to FIG. 23, the exposed gate photoresist film 1143 isdeveloped, using a developing agent, to form a gate photoresist pattern1143 a on the primary gate copper nitride layer 1144.

The primary gate conductive layer 1142, the primary gate barrier layer1141, and the primary gate copper nitride layer 1144 are partiallyetched, using the gate photoresist pattern 1143 a as an etching mask, toform the gate line 1131 and the gate electrode 1118 on the insulatingsubstrate 120.

The gate copper nitride layer 1131 c of the gate line 1131 may havesubstantially the same etching rate as the copper of the gate conductivelayer 1131 b, thereby improving the etching uniformity of the gate line1131. For example, when a molybdenum layer (not shown) on a gateconductive layer having a different etching rate than the gateconductive layer is formed on a gate conductive layer, the molybdenumlayer may be over-etched such that a portion of the gate conductivelayer may be exposed. However, in FIG. 23, the gate copper nitride layer1131 c has substantially the same etching rate as the gate conductivelayer 1131 b, thereby improving the etching profile of the gate line1131.

The gate photoresist pattern 143 a is removed from the gate line 1131and the gate electrode 1118.

Referring to FIG. 24, a gate insulating layer 126 is formed on theinsulating substrate 120 to cover the gate line 1131 and the gateelectrode 1118.

An amorphous silicon pattern 137 a is formed on the gate insulatinglayer corresponding to the gate electrode 1118. A primary n+ amorphoussilicon pattern 137 c is formed on the amorphous silicon pattern 137 a.

Referring to FIG. 25, a primary data barrier layer (not shown) and aprimary data conductive layer (not shown) are formed on the gateinsulating layer 126, on which the amorphous silicon pattern 137 a andthe primary n+ amorphous silicon pattern 137 c (shown in FIG. 24) areformed, in sequence. A primary data copper nitride layer (not shown) isdeposited on the primary data conductive layer. For example, the primarydata copper nitride layer may be deposited through a sputtering process.A data photoresist film (not shown) may be formed on the primary datacopper nitride layer.

The primary data barrier layer, the primary data conductive layer, andthe primary data copper nitride layer are partially etched through aphotolithography process using a data mask (not shown) to form the dataline 1133, the source electrode 1117, and the drain electrode 1119 onthe gate insulating layer 126. Alternatively, nitride plasma may beimplanted into each of the data line 1133, the source electrode 1117,and the drain electrode 1119 to form a copper nitride layer (not shown)on each of a side surface of the data conductive layer 1133 b of thedata line 1133, a side surface of the source conductive pattern 1117 bof the source electrode 1117, and a side surface of the drain conductivepattern 1119 b of the drain electrode 1119.

The primary n+ amorphous silicon pattern 137 c (shown in FIG. 24)interposed between the source electrode 1117 and the drain electrode1119 is partially etched, using the source electrode 1117 and the drainelectrode 1119 as an etching mask, so that the amorphous silicon pattern137 a is partially exposed between the source electrode 1117 and thedrain electrode 1119. Also, the primary n+ amorphous silicon pattern 137c is divided into two patterns spaced apart from each other andcorresponding to the source electrode 1117 and the drain electrode 1119.

Referring to FIG. 26, the passivation layer 116 is formed on the gateinsulating layer 126 to cover the semiconductor pattern 137, the dataline 1133, the source electrode 1117, and the drain electrode 1119. Thepassivation layer 116 is partially etched to form a contact hole 151through which the drain electrode 1119 is partially exposed.

The pixel electrode 112 is connected to the drain electrode 1119 throughthe contact hole 151 and is formed on the passivation layer 116 havingthe contact hole 151.

According to the method of manufacturing the array substrate of FIG. 22,FIG. 23, FIG. 24, FIG. 25, and FIG. 26, each of the gate line 1131, thegate electrode 1118, the data line 1133, the source electrode 1117, andthe drain electrode 1119 includes a copper nitride layer that hassubstantially the same etching rate as the copper of the gate conductivelayer 1131 b, which may improve the etching profile of the gate line1131, the gate electrode 1118, the data line 1133, the source electrode1117, and the drain electrode 1119. Thus, the occurrence of defects inthe array substrate may be decreased.

FIG. 27 is a cross-sectional view showing an array substrate inaccordance with another embodiment of the present invention. The arraysubstrate of FIG. 27 is substantially the same as in FIG. 21 except forthe data line, the source electrode, and the drain electrode. Thus, thesame reference numerals will be used to refer to the same or like partsand any further explanation concerning the above elements will beomitted.

Referring to FIG. 27, the data line 533 includes a data barrier layer533 a, a data conductive layer 533 b, a data copper nitride layer 533 c,and a side copper nitride layer 533 d.

The data copper nitride layer 533 c is disposed on an upper surface ofthe data conductive layer 533 b to protect the data line 533 duringsubsequent processes. The subsequent processes may include an etchingprocess for forming an n+ amorphous silicon pattern 137 b, a cleaningprocess, and a deposition process.

The side copper nitride layer 533 d is disposed on a side surface of thedata conductive layer 533 b to protect the data line 533 during thesubsequent processes. For example, the side copper nitride layer 533 dprotects the data line 533 during the etching process for forming the n+amorphous silicon pattern 137 b such that the data line 533 may not beetched by an etchant for etching a primary n+ amorphous silicon pattern.

The source electrode 517 is formed on substantially the same layer asthe data line 533. The source electrode 517 includes a source barrierpattern 517 a, a source conductive pattern 517 b, a source coppernitride pattern 517 c, and a first side surface copper nitride pattern517 d.

The source copper nitride pattern 517 c is disposed on an upper surfaceof the source conductive pattern 517 b.

The first side copper nitride pattern 517 d is disposed on a sidesurface of the source conductive pattern 517 b to protect the sourceelectrode 517 during the etching process for forming the n+ amorphoussilicon pattern 137 b.

The drain electrode 519 is formed on substantially the same layer as thedata line 533. The drain electrode 519 includes a drain barrier pattern519 a, a drain conductive pattern 519 b, a drain copper nitride pattern519 c, and a second copper nitride pattern 519 d.

The drain copper nitride pattern 519 c is disposed on an upper surfaceof the drain conductive pattern 519 b.

The second side copper nitride pattern 519 d is disposed on a sidesurface of the drain conductive pattern 519 b to protect the sourceelectrode 519 during the etching process for forming the n+ amorphoussilicon pattern 137 b. The second side copper nitride pattern 519 d mayprotect the source electrode 519 during subsequent processes includingthe cleaning process and the deposition process.

The data copper nitride layer 533 c, the source copper nitride pattern517 c, and the drain copper nitride pattern 519 c of FIG. 27 may beformed through substantially the same sputtering process as describedwith respect to FIG. 25. The side copper nitride layer 533 d, the firstside copper nitride pattern 517 d, and the second side copper nitridepattern 519 d of FIG. 27 may be formed using substantially the samenitride plasma as described with respect to FIG. 16. Alternatively, eachof the upper and side surfaces of the data line 533, the sourceelectrode 517, and the drain electrode 519 may be covered by a coppernitride layer.

Accordingly, in the array substrate of FIG. 27, the etching uniformityof the data line 533, the source electrode 517, and the drain electrode519 may be improved, which may increase the yield of the arraysubstrate.

FIG. 28 is a cross-sectional view showing an array substrate inaccordance with another exemplary embodiment of the present invention.

Referring to FIG. 28, the array substrate includes an insulatingsubstrate 220, a data line 233, a gate line 231, a thin film transistor255, a gate insulating layer 226, a passivation layer 216, and a pixelelectrode 212. Alternatively, the array substrate may include aplurality of data lines, a plurality of gate lines, a plurality of thinfilm transistors, and a plurality of pixel electrodes.

The data line 233 includes a data barrier layer 233 a, a data conductivelayer 233 b, and a data copper nitride layer 233 c. The data barrierlayer 233 a is disposed on the insulating substrate 220 and the dataconductive layer 233 b is disposed on the data barrier layer 233 a. Thedata copper nitride layer 233 c is disposed on an upper surface and aside surface of the data conductive layer 233 b.

A source electrode 217 of the thin film transistor 255 is formed onsubstantially the same layer as the data line 233 and is connected tothe data line 233.

The source electrode 217 includes a source barrier pattern 217 a, asource conductive pattern 217 b, and a source copper nitride pattern 217c. The source copper nitride pattern 217 c is disposed on an uppersurface and a side surface of the source conductive pattern 217 b.

A drain electrode 219 of the thin film transistor 255 is formed fromsubstantially the same layer as the data line 233. The drain electrode219 is spaced apart from the source electrode 217.

The drain electrode 219 includes a drain barrier pattern 219 a, a drainconductive pattern 219 b, and a drain copper nitride pattern 219 c. Thedrain copper nitride pattern 219 c is disposed on an upper surface and aside surface of the drain conductive pattern 219 b.

A semiconductor pattern 237 of the thin film transistor 255 isinterposed between the source electrode 217 and the drain electrode 219.The semiconductor pattern 237 includes an n+ amorphous silicon pattern237 b and an amorphous silicon pattern 237 a. The n+ amorphous siliconpattern 237 b includes a first pattern on the source electrode 217 and asecond pattern on the drain electrode 219. The amorphous silicon pattern234 a is disposed on the n+ amorphous silicon pattern 237 b and theportion of the insulating substrate 220 between the source electrode 217and the drain electrode 219.

The gate insulating layer 226 is disposed on the insulating substrate220 and covers the data line 233, the source electrode 217, the drainelectrode 219, and the semiconductor pattern 237. The gate insulatinglayer 226 and the passivation layer 216 have a contact hole 251 throughwhich the drain electrode 219 is partially exposed.

A gate electrode 218 of the thin film transistor 255 is disposed on thegate insulating layer 226 corresponding to the semiconductor pattern237. The gate electrode 218 includes a gate barrier pattern 218 a, agate conductive pattern 218 b, and a gate copper nitride pattern 218 c.The gate copper nitride pattern 218 c is disposed on an upper surfaceand a side surface of the gate conductive pattern 218 b.

The gate line 231 is formed on substantially the same layer as the gateelectrode 218 and is connected to the gate electrode 218.

The gate line 231 includes a gate barrier layer 231 a, a gate conductivelayer 231 b, and a gate copper nitride layer 231 c. The gate conductivelayer 231 b is disposed on the gate barrier layer 231 a and the gatecopper nitride layer 231 c is disposed on an upper surface and a sidesurface of the gate conductive layer 231 b.

The passivation layer 216 is disposed on the gate insulating layer 226to cover the gate electrode 218 and the gate line 231. The drainelectrode 219 is partially exposed through the contact hole 251 formedin the passivation layer and the gate insulating layer 226.

The pixel electrode 212 is disposed on the passivation layer 216. Thepixel electrode 212 is connected to the drain electrode 219 through thecontact hole 251 formed in the passivation layer 216.

Accordingly, in the array substrate of FIG. 28, the resistance of thedata line 233 on the insulating substrate 220 and the gate line 231 onthe gate insulating layer 226 may be decreased, which may improve theimage display quality of a display device.

FIG. 29 is a cross-sectional view showing a display device in accordancewith another exemplary embodiment of the present invention.

Referring to FIG. 29, the display device includes an insulatingsubstrate 320, a black matrix 302, a gate line 331, a data line (notshown), a driving voltage line 333, a driving transistor 355, aswitching transistor (not shown), a gate insulating layer 326, apassivation layer 316, a color filter 304, a pixel electrode 312, anorganic light emitting layer 308, an opposite electrode 306, and aprotecting layer 305. Alternatively, the display device may include aplurality of gate lines, a plurality of data lines, a plurality ofdriving voltage lines, a plurality of driving transistors, a pluralityof switching transistors, a plurality of color filters, and a pluralityof pixel electrodes.

The black matrix 302 is formed on the insulating substrate 320 to blocklight. The black matrix 302 includes a plurality of openings 348arranged in a matrix. Each of the openings 348 of the black matrix 302may correspond to a pixel electrode 312.

The gate line 331 is disposed on the black matrix 302 and includes agate barrier layer 331 a, a gate conductive layer 331 b, and a gatecopper nitride layer 331 c. The gate conductive layer 331 b is disposedon the gate barrier layer 331 a. The gate copper nitride layer 331 c isdisposed on an upper surface and a side surface of the gate conductivelayer 331 b. The gate line 331 is connected to a gate electrode (notshown) of the switching transistor.

A gate electrode 318 of the driving transistor 355 is formed onsubstantially the same layer as the gate line 331. The gate electrode318 is connected to a drain electrode (not shown) of the switchingtransistor. The gate electrode 318 includes a gate barrier pattern 318a, a gate conductive pattern 318 b, and a gate copper nitride pattern318 c. The gate copper nitride pattern 318 c is disposed on an uppersurface and a side surface of the gate conductive pattern 318 b.

The gate insulating layer 326 is disposed on the insulating substrate320 on which the black matrix 302, the gate line 331, and the gateelectrode 318 are formed. In FIG. 29, the gate insulating layer 326includes a first gate insulating layer made of low density siliconnitride, a second gate insulating layer made of high density siliconnitride, and a third gate insulating layer made of low density siliconnitride.

A semiconductor pattern 337 of the driving transistor 355 is disposed onthe gate insulating layer 326 corresponding to the gate electrode 318.The semiconductor pattern 337 includes an amorphous silicon pattern 337a and an n+ amorphous silicon pattern 337 b.

The driving voltage line 333 is disposed on the gate insulating layer326. The driving voltage line 333 includes a driving voltage barrierlayer 333 a, a driving voltage conductive layer 333 b, and a drivingvoltage copper nitride layer 333 c. The driving voltage conductive layer333 b is disposed on the driving voltage barrier layer 333 a and thedriving voltage copper nitride layer 333 c is disposed on an uppersurface and a side surface of the driving voltage conductive layer 333b.

A source electrode 317 of the driving transistor 355 is disposed on thesemiconductor pattern 337. The source electrode 317 is electricallyconnected to the driving voltage line 333. The source electrode 317includes a source barrier pattern 317 a, a source conductive pattern 317b, and a source copper nitride pattern 317 c. The source copper nitridepattern 317 c is disposed on an upper surface and a side surface of thesource conductive pattern 317 b.

A drain electrode 319 of the driving transistor 355 is spaced apart fromthe source electrode 317 on the semiconductor pattern 337. The drainelectrode 319 includes a drain barrier pattern 319 a, a drain conductivepattern 319 b, and a drain copper nitride pattern 319 c. The draincopper nitride pattern 319 c is disposed on an upper surface and a sidesurface of the drain conductive pattern 319 b.

The passivation layer 316 is disposed on the gate insulating layer 326to cover the driving transistor 355, the switching transistor, and thedriving voltage line 333.

The color filter 304 is disposed on the passivation layer 316 totransmit colored light having a wavelength corresponding to the color.Alternatively, an overcoating layer (not shown) may be formed on thecolor filter 304. The passivation layer 316 and the color filter 304have a contact hole 351 through which the drain electrode 319 of thedriving transistor 355 is partially exposed.

The pixel electrode 312 is disposed on the color filter 304, and isconnected to the drain electrode 319 of the driving transistor 355through the contact hole 351. The pixel electrode 312 may include atransparent conductive material.

The organic light emitting layer 308 is formed on the color filter 304to cover the pixel electrode 312.

The opposite electrode 306 is disposed on the organic light emittinglayer 308 and may include metal.

The protecting layer 305 is formed on the opposite electrode 306 toprotect the opposite electrode 306.

When a current flows through the organic light emitting layer 308between the pixel electrode 312 and the opposite electrode 306, theorganic light emitting layer 308 generates light. The light generatedfrom the organic light emitting layer 308 passes through the colorfilter 304, thereby displaying an image.

Accordingly, in the display device of FIG. 29, the resistance of thegate line 331, the driving voltage line 333, and the data line (notshown) may be decreased, which may improve the image display quality ofthe display device. In addition, the etching resistance of the sourceelectrode 317 and the drain electrode 319 may be increased by the coppernitride patterns 317 c and 319 c that are formed on the side surfaces ofthe source and drain electrodes 317 and 319, which may decrease theoccurrence of defects in the display device.

According to the present invention, the copper nitride patterns areformed on the upper surface and the side surface of the conductivepatterns so that an additional protecting layer for protecting thecopper lines may be omitted. Thus, the manufacturing time and themanufacturing cost of the array substrate may be decreased.

In addition, the copper nitride pattern formed through a sputteringprocess has substantially the same etching rate as the conductivepattern, which may improve the etching profile of the conductivepatterns of the array substrate.

Furthermore, the copper nitride pattern formed through the nitrideplasma process covers the side surface of the conductive patterns toprotect the conductive patterns during the etching process for etchingthe n+ amorphous silicon pattern.

Also, since the resistance of the conductive patterns may be decreased,the image display quality of the display device may be improved.

The gate insulating layer may also have a multi-layered structure toimprove the electrical characteristics of the semiconductor pattern.

It will be apparent to those skilled in the art that variousmodifications and variations can be made in the present inventionwithout departing from the spirit or scope of the invention. Thus, it isintended that the present invention cover the modifications andvariations of this invention provided they come within the scope of theappended claims and their equivalents.

1. An array substrate, comprising: a switching element on an insulatingsubstrate; a signal transmission line connected to the switchingelement, the signal transmission line comprising: a barrier layer on theinsulating substrate; a conductive line on the barrier layer, theconductive line comprising copper or copper alloy; and a copper nitridelayer covering the conductive line.